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CY29940
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
Features
* * * * * * 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 18 clock outputs: drive up to 36 clock lines 60 ps typical output-to-output skew Dual or single supply operation: -- 3.3V core and 3.3V outputs -- 3.3V core and 2.5V outputs -- 2.5V core and 2.5V outputs * Pin compatible with MPC940L, MPC9109 * Available in Commercial and Industrial temperature * 32-pin LQFP package
Description
The CY29940 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS/LVTTL compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29940 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems.
Block Diagram
VDD PECL_CLK PECL_CLK# TCLK TCLK_SEL 0 1 VDDC
Pin Configuration
VDDC VSS 25 Q0 Q1 Q2 Q3 28 Q4 27 Q5 26
32
31
30
29
18
Q0-Q17
VSS VSS TCLK TCLK_SEL PECL_CLK PECL_CLK# VDD VDDC
1 2 3 4 5 6 7 8
CY29940
10 11 12 13 14 15 16 9
24 23 22 21 20 19 18 17
Q6 Q7 Q8 VDD Q9 Q10 Q11 VSS
VSS
Pin Description[1]
Pin 5 6 3 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 4 8, 16, 29 7, 21 1, 2, 12, 17, 25 Name PECL_CLK PECL_CLK# TCLK Q(17:0) VDDC PWR I/O I, PU I, PD I, PD O PECL Input Clock PECL Input Clock External Reference/Test Clock Input Clock Outputs Description
TCLK_SEL VDDC VDD VSS
I, PD
Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 3.3V or 2.5V Power Supply for Output Clock Buffers 3.3V or 2.5V Power Supply Common Ground
Note: 1. PD = Internal Pull-Down, PU = Internal Pull-up
Cypress Semiconductor Corporation Document #: 38-07283 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised April 4, 2006
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VDDC
Q17
Q16
Q15
Q14
Q13
Q12
CY29940
Maximum Ratings[2]
Maximum Input Voltage Relative to VSS: ............ VSS - 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum ESD Protection............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
DC Parameters[2]: VDD = 3.3V 5% or 2.5V 5%, VDDC = 3.3V 5% or 2.5V 5%, TA = -40C to +85C
Parameter VIL VIH IIL IIH VPP Description Input Low Voltage Input High Voltage Input Low Current Input High
[3]
Conditions
Min. VSS 2.0
Typ. - - - -
Max. 0.8 VDD -200 200 1000
Unit. V V A A mV
Current[3] 500
Peak-to-Peak Input Voltage PECL_CLK Common Mode Range[4] PECL_CLK Output Low Voltage[5, 6, 7] VDD = 3.3V VDD = 2.5V IOL = 20 mA IOH = -20 mA, VDDC = 3.3V IOH = -20 mA, VDDC = 2.5V
-
VCMR VOL VOH IDDQ IDD
VDD - 1.4 VDD - 1.0 - 2.4 1.8 -
- - - - - 5 285 335 200 240 12 15 4
VDD - 0.6 VDD - 0.6 0.5 - - 7 - - - - 16 20 -
V V V V V mA mA
Output High Voltage[5, 6, 7] Quiescent Supply Current Dynamic Supply Current
VDD = 3.3V, Outputs @ 150 MHz, CL = 15 pF VDD = 3.3V, Outputs @ 200 MHz, CL = 15 pF VDD = 2.5V, Outputs @ 150 MHz, CL = 15 pF VDD = 2.5V, Outputs @ 200 MHz, CL = 15 pF
- - - - 8 10 -
Zout Cin
Output Impedance Input Capacitance
VDD = 3.3V VDD = 2.5V
pF
Notes: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines 5. Outputs driving 50 transmission lines. 6. See Figure 1 &2. 7. 50% input duty cycle.
Document #: 38-07283 Rev. *C
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CY29940
AC Parameters[8]: VDD = 3.3V 5% or 2.5V 5%, VDDC = 3.3V 5% or 2.5V 5%, TA = -40C to +85C
Parameter Fmax tPD Description Input Frequency PECL_CLK to Q Delay[5, 6, 11] 134 MHz Output-to-Output Skew[5, 6] Part-to-Part Skew[9] Part-to-Part Skew[9] Part to Part Skew[10] VDD = 3.3V VDD = 2.5V PECL, VDDC = 3.3V PECL, VDDC = 2.5V TCLK, VDDC = 3.3V TCLK, VDDC = 2.5V PECL_CLK TCLK Output Clocks Rise/Fall Time[5, 6] 0.7V to 2.0V, VDDC = 3.3V 0.5V to 1.8V, VDDC = 2.5V Conditions - tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH Min. - 2.0 2.1 1.9 2.0 2.5 2.6 2.5 2.6 1.9 2.0 1.8 1.8 2.5 2.5 2.3 2.3 - - - - - - - - - - - 0.3 0.3 - - - - - - - - Typ. - - - - - - - - - - - - - - - - - - - - 60 Max. 200 3.2 3.4 3.1 3.2 5.2 5 5 5 3 3.2 2.9 3.1 4 4 3.8 3.8 10 55 60 150 200 1.4 2.2 1.2 1.7 850 750 1.1 1.2 ns ps ns ns ps ps % ns Unit. MHz ns
Notes: 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 9. Across temperature and voltage ranges, includes output skew. 10. For a specific temperature and voltage, includes output skew 11. Parameters tested @ 150 MHz.
Document #: 38-07283 Rev. *C
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CY29940
CY29940 DUT
Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK CY29940 Test Reference for VCC = 3.3V and VCC = 2.5V
Zo = 50 ohm Differential Pulse Generator Z = 50 ohm
CY29940 DUT
Zo = 50 ohm
Zo = 50 ohm RT = 50 ohm RT = 50 ohm
VTT
VTT
Figure 2. PECL_CLK CY29940 Test Reference for VCC = 3.3V and VCC = 2.5V
PECL_CLK PECL_CLK
VPP
VCMR
VCC VCC /2
tP
VCC
GND
Q
VCC /2
T0 DC = tP / T0 x 100%
Figure 5. Output Duty Cycle (FoutDC)
tPD
GND
Figure 3. Propagation Delay (TPD) Test Reference
LVCMOS_CLK
VCC
VCC
VCC /2 GND VCC
VCC /2 GND VCC VCC /2
Q
VCC /2
tPD
GND
tSK(0)
Figure 6. Output-to-Output Skew tsk(0)
GND
Figure 4. LVCMOS Propagation Delay (TPD) Test Reference
Document #: 38-07283 Rev. *C
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CY29940
Ordering Information
Part Number
CY29940AI CY29940AIT CY29940AC CY29940ACT
Package Type
32 Pin LQFP 32 Pin LQFP - Tape and Reel 32 Pin LQFP 32 Pin LQFP - Tape and Reel 32 Pin LQFP 32 Pin LQFP - Tape and Reel 32 Pin LQFP 32 Pin LQFP - Tape and Reel
Production Flow
Industrial, -40C to +85C Industrial, -40C to +85C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to +85C Industrial, -40C to +85C Commercial, 0C to 70C Commercial, 0C to 70C
Lead-free
CY29940AXI CY29940AXIT CY29940AXC CY29940AXCT
Document #: 38-07283 Rev. *C
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CY29940
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
All product and company names mentioned in this document may be the trademarks of their respective owners.
Document #: 38-07283 Rev. *C
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY29940
Document History Page
Document Title: CY29940 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Document Number: 38-07283 REV.
** *A
ECN NO.
111094 116776
Issue Date
02/01/02 08/15/02
Orig. of Change
BRK HWT New data sheet
Description of Change
Incorporate results of final characterization using corporate methods, added output impedance on page 3 and added output duty cycle on page 4. Add commercial temperature range in the ordering information on page 6. Add power up requirements to maximum rating information Add typical value for output-to-output skew Add Lead-free devices
*B *C
122875 448379
12/21/02 See ECN
RBI RGL
Document #: 38-07283 Rev. *C
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